mirror of
https://github.com/HorlogeSkynet/archey4
synced 2024-11-24 04:00:10 +01:00
383 lines
10 KiB
Python
383 lines
10 KiB
Python
"""Test module for Archey's CPU detection module"""
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import unittest
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from unittest.mock import mock_open, patch
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from archey.entries.cpu import CPU
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from archey.test import CustomAssertions
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from archey.test.entries import HelperMethods
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class TestCPUEntry(unittest.TestCase, CustomAssertions):
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"""
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Here, we mock the `open` call on `/proc/cpuinfo` with fake content.
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In some cases, `lscpu` output is being mocked too.
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"""
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@patch(
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"archey.entries.cpu.open",
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mock_open(
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read_data="""\
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processor\t: 0
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vendor_id\t: CPU-VENDOR-NAME
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cpu family\t: X
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model\t\t: YY
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model name\t: CPU-MODEL-NAME
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physical id\t: 0
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"""
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),
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)
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def test_parse_proc_cpuinfo_one_entry(self):
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"""Test `/proc/cpuinfo` parsing"""
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self.assertListEqual(
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CPU._parse_proc_cpuinfo(), # pylint: disable=protected-access
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[{"CPU-MODEL-NAME": 1}],
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)
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@patch(
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"archey.entries.cpu.open",
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mock_open(
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read_data="""\
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processor\t: 0
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vendor_id\t: CPU-VENDOR-NAME
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cpu family\t: X
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model\t\t: YY
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model name\t: CPU-MODEL-NAME
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physical id\t: 0
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processor\t: 1
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vendor_id\t: CPU-VENDOR-NAME
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cpu family\t: X
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model\t\t: YY
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model name\t: ANOTHER-CPU-MODEL
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physical id\t: 1
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processor\t: 2
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vendor_id\t: CPU-VENDOR-NAME
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cpu family\t: X
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model\t\t: YY
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model name\t: ANOTHER-CPU-MODEL
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physical id\t: 1
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"""
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),
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)
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def test_parse_proc_cpuinfo_multiple_entries(self):
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"""Test `/proc/cpuinfo` parsing"""
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self.assertListEqual(
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CPU._parse_proc_cpuinfo(), # pylint: disable=protected-access
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[{"CPU-MODEL-NAME": 1}, {"ANOTHER-CPU-MODEL": 2}],
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)
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@patch(
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"archey.entries.cpu.open",
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mock_open(
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read_data="""\
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processor\t: 0
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vendor_id\t: CPU-VENDOR-NAME
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cpu family\t: X
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model\t\t: YY
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model name\t: CPU-MODEL-NAME
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physical id\t: 0
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processor\t: 1
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vendor_id\t: CPU-VENDOR-NAME
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cpu family\t: X
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model\t\t: YY
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model name\t: CPU-MODEL-NAME
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physical id\t: 1
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processor\t: 2
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vendor_id\t: CPU-VENDOR-NAME
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cpu family\t: X
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model\t\t: YY
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model name\t: CPU-MODEL-NAME
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physical id\t: 0
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processor\t: 3
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vendor_id\t: CPU-VENDOR-NAME
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cpu family\t: X
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model\t\t: YY
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model name\t: CPU-MODEL-NAME
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physical id\t: 1
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"""
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),
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)
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def test_parse_proc_cpuinfo_one_cpu_dual_socket(self):
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"""Test `/proc/cpuinfo` parsing for same CPU model across two sockets"""
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self.assertListEqual(
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CPU._parse_proc_cpuinfo(), # pylint: disable=protected-access
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[{"CPU-MODEL-NAME": 2}, {"CPU-MODEL-NAME": 2}],
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)
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@patch(
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"archey.entries.cpu.open",
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mock_open(
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read_data="""\
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processor\t: 0
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vendor_id\t: CPU-VENDOR-NAME
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cpu family\t: X
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model\t\t: YY
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model name\t: CPU-MODEL-NAME
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physical id\t: 0
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processor\t: 1
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vendor_id\t: CPU-VENDOR-NAME
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cpu family\t: X
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model\t\t: YY
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model name\t: ANOTHER-CPU-MODEL
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physical id\t: 0
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processor\t: 2
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vendor_id\t: CPU-VENDOR-NAME
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cpu family\t: X
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model\t\t: YY
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model name\t: ANOTHER\tCPU MODEL WITH STRANGE S P A C E S
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physical id\t: 1
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processor\t: 3
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vendor_id\t: CPU-VENDOR-NAME
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cpu family\t: X
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model\t\t: YY
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model name\t: ANOTHER\tCPU MODEL WITH STRANGE S P A C E S
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physical id\t: 1
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"""
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),
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)
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def test_parse_proc_cpuinfo_multiple_inconsistent_entries(self):
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"""
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Test `/proc/cpuinfo` parsing with multiple CPUs sharing same physical ids (unlikely).
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Also check our model name normalizations applied on white characters.
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"""
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self.assertListEqual(
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CPU._parse_proc_cpuinfo(), # pylint: disable=protected-access
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[
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{"CPU-MODEL-NAME": 1, "ANOTHER-CPU-MODEL": 1},
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{"ANOTHER CPU MODEL WITH STRANGE S P A C E S": 2},
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],
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)
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@patch("archey.entries.cpu.open", side_effect=PermissionError())
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def test_parse_proc_cpuinfo_unreadable_file(self, _):
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"""Check behavior when `/proc/cpuinfo` could not be read from disk"""
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self.assertListEmpty(CPU._parse_proc_cpuinfo()) # pylint: disable=protected-access
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@patch(
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"archey.entries.cpu.check_output",
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side_effect=[
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FileNotFoundError(),
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"""\
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{
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"SPHardwareDataType" : [
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{
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"_name" : "hardware_overview",
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"cpu_type" : "Dual-Core Intel Core i5",
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"current_processor_speed" : "3,1 GHz",
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"machine_model" : "MacBookPro00OOooOO00",
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"machine_name" : "MacBook Pro",
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"number_processors" : 2,
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"packages" : 1,
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"platform_cpu_htt" : "htt_enabled",
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"platform_UUID" : "XXXXXXXX-YYYY-ZZZZ-TTTT-UUUUUUUUUUUU",
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"provisioning_UDID" : "XXXXXXXX-YYYY-ZZZZ-TTTT-UUUUUUUUUUUU",
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"serial_number" : "XX00YY11ZZ22"
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}
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]
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}
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""",
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],
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)
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def test_parse_system_profiler(self, _):
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"""Check `_parse_system_profiler` behavior"""
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# pylint: disable=protected-access
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self.assertListEmpty(CPU._parse_system_profiler())
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self.assertListEqual(
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CPU._parse_system_profiler(),
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[{"Dual-Core Intel Core i5 @ 3.1 GHz": 4}],
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)
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# pylint: enable=protected-access
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@patch(
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"archey.entries.cpu.check_output",
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side_effect=[
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FileNotFoundError(),
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"""\
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Intel(R) Core(TM) i5-7267U CPU @ 3.10GHz
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8
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""",
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],
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)
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def test_parse_sysctl_machdep(self, _):
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"""Check `_parse_sysctl_machdep` behavior"""
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# pylint: disable=protected-access
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self.assertListEmpty(CPU._parse_sysctl_machdep())
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self.assertListEqual(
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CPU._parse_sysctl_machdep(),
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[{"Intel(R) Core(TM) i5-7267U CPU @ 3.10GHz": 8}],
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)
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# pylint: enable=protected-access
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@patch(
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"archey.entries.cpu.check_output",
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side_effect=[
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"""\
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Architecture: x86_64
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CPU op-mode(s): 32-bit, 64-bit
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Byte Order: Little Endian
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CPU(s): 4
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On-line CPU(s) list: 0-3
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Thread(s) per core: 1
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Core(s) per socket: 4
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Socket(s): 1
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NUMA node(s): 1
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Vendor ID: CPU-VENDOR-NAME
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CPU family: Z
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Model: \xde\xad\xbe\xef
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Model name: CPU-MODEL-NAME
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""",
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"""\
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Architecture: x86_64
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CPU op-mode(s): 32-bit, 64-bit
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Byte Order: Little Endian
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CPU(s): 2
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On-line CPU(s) list: 0-1
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Thread(s) per core: 1
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Core(s) per socket: 2
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Socket(s): 1
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NUMA node(s): 1
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Vendor ID: CPU-VENDOR-NAME
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CPU family: Z
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Model: \xde\xad\xbe\xef
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Model name: CPU-MODEL-NAME
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Architecture: x86_64
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CPU op-mode(s): 32-bit, 64-bit
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Byte Order: Little Endian
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CPU(s): 4
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On-line CPU(s) list: 0-3
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Thread(s) per core: 2
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Core(s) per socket: 2
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Socket(s): 1
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NUMA node(s): 1
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Vendor ID: CPU-VENDOR-NAME
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CPU family: Z
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Model: \xde\xad\xbe\xef
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Model name: ANOTHER-CPU-MODEL
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""",
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"""\
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Architecture: x86_64
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CPU op-mode(s): 32-bit, 64-bit
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Byte Order: Little Endian
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CPU(s): 16
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On-line CPU(s) list: 0-15
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Thread(s) per core: 2
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Core(s) per socket: 4
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Socket(s): 2
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NUMA node(s): 2
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Vendor ID: CPU-VENDOR-NAME
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CPU family: Z
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Model: \xde\xad\xbe\xef
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Model name: CPU-MODEL-NAME
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""",
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"""\
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Architecture: aarch64
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CPU op-mode(s): 32-bit, 64-bit
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Byte Order: Little Endian
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CPU(s): 4
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On-line CPU(s) list: 0-3
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Vendor ID: ARM
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Model name: Cortex-A72
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Model: 3
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Thread(s) per core: 1
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Core(s) per cluster: 4
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Socket(s): -
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Cluster(s): 1
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""",
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],
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)
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def test_parse_lscpu_output(self, _):
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"""
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Test model name parsing from `lscpu` output.
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See issues #29 and #127 (ARM architectures).
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`/proc/cpuinfo` will not contain `model name` (nor `physical id`) info.
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`lscpu` output will be used instead.
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"""
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with self.subTest("Simple unique CPU."):
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self.assertListEqual(
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CPU._parse_lscpu_output(), # pylint: disable=protected-access
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[{"CPU-MODEL-NAME": 4}],
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)
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with self.subTest("Two CPUs, 1 socket."):
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self.assertListEqual(
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CPU._parse_lscpu_output(), # pylint: disable=protected-access
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[{"CPU-MODEL-NAME": 2}, {"ANOTHER-CPU-MODEL": 4}],
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)
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with self.subTest("1 CPU, 2 sockets."):
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self.assertListEqual(
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CPU._parse_lscpu_output(), # pylint: disable=protected-access
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[{"CPU-MODEL-NAME": 8}, {"CPU-MODEL-NAME": 8}],
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)
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with self.subTest("4 CPUs, 1 cluster."):
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self.assertListEqual(
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CPU._parse_lscpu_output(), # pylint: disable=protected-access
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[{"Cortex-A72": 4}],
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)
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@HelperMethods.patch_clean_configuration
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def test_various_output_configuration(self):
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"""
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Test `__iter__` and `__next__` output overloading based on user preferences combination
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"""
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cpu_instance_mock = HelperMethods.entry_mock(CPU)
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cpu_instance_mock.value = [{"CPU-MODEL-NAME": 1}, {"ANOTHER-CPU-MODEL": 2}]
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with self.subTest("Normal output."):
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cpu_instance_mock.options["one_line"] = True
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self.assertListEqual(
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list(cpu_instance_mock),
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[("CPU", "CPU-MODEL-NAME"), ("CPU", "2 x ANOTHER-CPU-MODEL")],
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)
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with self.subTest("Normal output (no count)."):
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cpu_instance_mock.options["show_cores"] = False
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cpu_instance_mock.options["one_line"] = True
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self.assertListEqual(
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list(cpu_instance_mock),
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[("CPU", "CPU-MODEL-NAME"), ("CPU", "ANOTHER-CPU-MODEL")],
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)
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with self.subTest("No CPU detected output."):
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cpu_instance_mock.value = []
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self.assertListEqual(
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list(cpu_instance_mock),
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[],
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)
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@patch(
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"archey.entries.cpu.check_output",
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side_effect=[
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FileNotFoundError(),
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"""\
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Intel(R) Core(TM) i5-5300U CPU @ 2.30GHz
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4
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""",
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],
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)
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def test_parse_sysctl_cpu_model(self, _):
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"""Check `_parse_sysctl_cpu_model` behavior"""
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# pylint: disable=protected-access
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self.assertListEmpty(CPU._parse_sysctl_cpu_model())
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self.assertListEqual(
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CPU._parse_sysctl_machdep(),
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[{"Intel(R) Core(TM) i5-5300U CPU @ 2.30GHz": 4}],
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)
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# pylint: enable=protected-access
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if __name__ == "__main__":
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unittest.main()
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