mirror of
https://github.com/HorlogeSkynet/archey4
synced 2025-05-17 16:00:13 +02:00
[CPU] Reworks entry to correctly deal with dual sockets CPUs
> Now compatible against Python < 3.6 > Caution : new proposal so still API-breaking
This commit is contained in:
Samuel FORESTIER
parent
25b9c47e69
commit
308b41ad7f
archey
@ -12,15 +12,27 @@ class CPU(Entry):
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Parse `/proc/cpuinfo` file to retrieve model names.
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If no information could be retrieved, call `lscpu`.
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`value` attribute is populated as a `dict`.
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It means that for Python < 3.6, "physical" CPU order **MAY** be lost.
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`value` attribute is populated as a `list` of `dict`.
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Each `dict` **SHOULD** contain only one entry (CPU model name as key and cores count as value).
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"""
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_MODEL_NAME_REGEXP = re.compile(
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r'^model name\s*:\s*(.*)$',
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flags=re.IGNORECASE | re.MULTILINE
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)
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_CPUS_COUNT_REGEXP = re.compile(
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r'^CPU\(s\)\s*:\s*(\d+)$',
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_PHYSICAL_ID_REGEXP = re.compile(
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r'^physical id\s*:\s*(\d+)$',
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flags=re.IGNORECASE | re.MULTILINE
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)
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_THREADS_PER_CORE_REGEXP = re.compile(
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r'^Thread\(s\) per core\s*:\s*(\d+)$',
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flags=re.IGNORECASE | re.MULTILINE
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)
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_CORES_PER_SOCKET_REGEXP = re.compile(
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r'^Core\(s\) per socket\s*:\s*(\d+)$',
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flags=re.IGNORECASE | re.MULTILINE
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)
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_SOCKETS_REGEXP = re.compile(
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r'^Socket\(s\)\s*:\s*(\d+)$',
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flags=re.IGNORECASE | re.MULTILINE
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)
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@ -40,22 +52,29 @@ class CPU(Entry):
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"""Read `/proc/cpuinfo` and search for CPU model names occurrences"""
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try:
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with open('/proc/cpuinfo') as f_cpu_info:
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cpu_models = cls._MODEL_NAME_REGEXP.findall(f_cpu_info.read())
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cpu_info = f_cpu_info.read()
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except (PermissionError, FileNotFoundError):
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return {}
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return []
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model_names = cls._MODEL_NAME_REGEXP.findall(cpu_info)
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physical_ids = cls._PHYSICAL_ID_REGEXP.findall(cpu_info)
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cpus_list = []
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# Manually de-duplicates CPUs count.
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cpu_info = {}
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for cpu_model in cpu_models:
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for model_name, physical_id in zip(model_names, physical_ids):
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# Sometimes CPU model names contain extra ugly white-spaces.
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cpu_model = re.sub(r'\s+', ' ', cpu_model)
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model_name = re.sub(r'\s+', ' ', model_name)
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if cpu_model not in cpu_info:
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cpu_info[cpu_model] = 1
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else:
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cpu_info[cpu_model] += 1
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try:
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cpus_list[int(physical_id)][model_name] += 1
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except KeyError:
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# Different CPUs with same physical ids ? Shouldn't happen.
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cpus_list[int(physical_id)][model_name] = 1
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except IndexError:
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cpus_list.append({model_name: 1})
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return cpu_info
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return cpus_list
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@classmethod
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def _parse_lscpu_output(cls):
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@ -65,38 +84,43 @@ class CPU(Entry):
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env={'LANG': 'C'}, universal_newlines=True
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)
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cpu_models = cls._MODEL_NAME_REGEXP.findall(cpu_info)
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cpu_counts = cls._CPUS_COUNT_REGEXP.findall(cpu_info)
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nb_threads = cls._THREADS_PER_CORE_REGEXP.findall(cpu_info)
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nb_cores = cls._CORES_PER_SOCKET_REGEXP.findall(cpu_info)
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nb_sockets = cls._SOCKETS_REGEXP.findall(cpu_info)
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model_names = cls._MODEL_NAME_REGEXP.findall(cpu_info)
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return {
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# Sometimes CPU model names contain extra ugly white-spaces.
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re.sub(r'\s+', ' ', cpu_model): int(cpu_count)
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for cpu_model, cpu_count in zip(cpu_models, cpu_counts)
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}
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cpus_list = []
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for threads, cores, sockets, model_name in zip(
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nb_threads, nb_cores, nb_sockets, model_names
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):
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for _ in range(int(sockets)):
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# Sometimes CPU model names contain extra ugly white-spaces.
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cpus_list.append(
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{re.sub(r'\s+', ' ', model_name): int(threads) * int(cores)}
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)
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return cpus_list
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def output(self, output):
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"""Writes CPUs to `output` based on preferences"""
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def _pre_format(cpu_model, cpu_count):
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"""Simple closure to format our CPU final entry content"""
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if cpu_count > 1 and self.options.get('show_count', True):
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return '{} x {}'.format(cpu_count, cpu_model)
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return cpu_model
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# No CPU could be detected.
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if not self.value:
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output.append(self.name, self._default_strings.get('not_detected'))
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# One-line output is enabled : Join the results !
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elif self.options.get('one_line', True):
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output.append(
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self.name,
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', '.join([
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_pre_format(cpu_model, cpu_count)
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for cpu_model, cpu_count in self.value.items()
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])
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)
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# One-line output has been disabled, add one entry per item.
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return
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entries = []
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for cpus in self.value:
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for model_name, cpu_count in cpus.items():
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if cpu_count > 1 and self.options.get('show_count', True):
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entries.append('{} x {}'.format(cpu_count, model_name))
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else:
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entries.append(model_name)
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if self.options.get('one_line', True):
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# One-line output is enabled : Join the results !
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output.append(self.name, ', '.join(entries))
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else:
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for cpu_model, cpu_count in self.value.items():
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output.append(self.name, _pre_format(cpu_model, cpu_count))
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# One-line output has been disabled, add one entry per item.
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for entry in entries:
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output.append(self.name, entry)
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@ -1,15 +1,15 @@
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"""Test module for Archey's CPU detection module"""
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import sys
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import unittest
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from unittest.mock import MagicMock, call, mock_open, patch
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from archey.entries.cpu import CPU
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from archey.test import CustomAssertions
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from archey.test.entries import HelperMethods
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from archey.constants import DEFAULT_CONFIG
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class TestCPUEntry(unittest.TestCase):
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class TestCPUEntry(unittest.TestCase, CustomAssertions):
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"""
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Here, we mock the `open` call on `/proc/cpuinfo` with fake content.
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In some cases, `lscpu` output is being mocked too.
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@ -23,14 +23,15 @@ vendor_id\t: CPU-VENDOR-NAME
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cpu family\t: X
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model\t\t: YY
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model name\t: CPU-MODEL-NAME
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physical id\t: 0
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"""),
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create=True
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)
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def test_model_name_match_cpuinfo(self):
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def test_parse_proc_cpuinfo_one_entry(self):
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"""Test `/proc/cpuinfo` parsing"""
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self.assertDictEqual(
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CPU().value,
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{'CPU-MODEL-NAME': 1}
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self.assertListEqual(
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CPU._parse_proc_cpuinfo(), # pylint: disable=protected-access
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[{'CPU-MODEL-NAME': 1}]
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)
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@patch(
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@ -42,29 +43,32 @@ vendor_id\t: CPU-VENDOR-NAME
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cpu family\t: X
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model\t\t: YY
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model name\t: CPU-MODEL-NAME
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physical id\t: 0
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processor\t: 0
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processor\t: 1
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vendor_id\t: CPU-VENDOR-NAME
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cpu family\t: X
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model\t\t: YY
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model name\t: ANOTHER-CPU-MODEL
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physical id\t: 1
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processor\t: 0
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processor\t: 2
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vendor_id\t: CPU-VENDOR-NAME
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cpu family\t: X
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model\t\t: YY
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model name\t: ANOTHER-CPU-MODEL
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physical id\t: 1
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"""),
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create=True
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)
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def test_multiple_cpus_from_proc_cpuinfo(self):
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def test_parse_proc_cpuinfo_multiple_entries(self):
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"""Test `/proc/cpuinfo` parsing"""
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self.assertDictEqual(
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CPU().value,
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{
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'CPU-MODEL-NAME': 1,
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'ANOTHER-CPU-MODEL': 2
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}
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self.assertListEqual(
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CPU._parse_proc_cpuinfo(), # pylint: disable=protected-access
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[
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{'CPU-MODEL-NAME': 1},
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{'ANOTHER-CPU-MODEL': 2}
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]
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)
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@patch(
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@ -75,37 +79,40 @@ processor\t: 0
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vendor_id\t: CPU-VENDOR-NAME
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cpu family\t: X
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model\t\t: YY
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model name\t: CPU-MODEL-NAME
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physical id\t: 0
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processor\t: 1
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vendor_id\t: CPU-VENDOR-NAME
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cpu family\t: X
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model\t\t: YY
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model name\t: CPU-MODEL-NAME
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physical id\t: 1
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processor\t: 2
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vendor_id\t: CPU-VENDOR-NAME
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cpu family\t: X
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model\t\t: YY
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model name\t: CPU-MODEL-NAME
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physical id\t: 0
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processor\t: 3
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vendor_id\t: CPU-VENDOR-NAME
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cpu family\t: X
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model\t\t: YY
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model name\t: CPU-MODEL-NAME
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physical id\t: 1
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"""),
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create=True
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)
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@patch(
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'archey.entries.cpu.check_output',
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return_value="""\
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Architecture: x86_64
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CPU op-mode(s): 32-bit, 64-bit
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Byte Order: Little Endian
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CPU(s): 4
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On-line CPU(s) list: 0-3
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Thread(s) per core: X
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Core(s) per socket: Y
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Socket(s): 1
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NUMA node(s): 1
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Vendor ID: CPU-VENDOR-NAME
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CPU family: Z
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Model: \xde\xad\xbe\xef
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Model name: CPU-MODEL-NAME-WITHOUT-PROC-CPUINFO
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""")
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def test_model_name_match_lscpu(self, _):
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"""
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Test model name parsing from `lscpu` output.
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See issue #29 (ARM architectures).
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`/proc/cpuinfo` will not contain `model name` info.
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`lscpu` output will be used instead.
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"""
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self.assertDictEqual(
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CPU().value,
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{'CPU-MODEL-NAME-WITHOUT-PROC-CPUINFO': 4}
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def test_parse_proc_cpuinfo_one_cpu_dual_socket(self):
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"""Test `/proc/cpuinfo` parsing for same CPU model across two sockets"""
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self.assertListEqual(
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CPU._parse_proc_cpuinfo(), # pylint: disable=protected-access
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[
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{'CPU-MODEL-NAME': 2},
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{'CPU-MODEL-NAME': 2}
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]
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)
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@patch(
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@ -116,15 +123,48 @@ processor\t: 0
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vendor_id\t: CPU-VENDOR-NAME
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cpu family\t: X
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model\t\t: YY
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model name\t: CPU MODEL\t NAME
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model name\t: CPU-MODEL-NAME
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physical id\t: 0
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processor\t: 1
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vendor_id\t: CPU-VENDOR-NAME
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cpu family\t: X
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model\t\t: YY
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model name\t: ANOTHER-CPU-MODEL
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physical id\t: 0
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processor\t: 2
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vendor_id\t: CPU-VENDOR-NAME
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cpu family\t: X
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model\t\t: YY
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model name\t: ANOTHER\tCPU MODEL WITH STRANGE S P A C E S
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physical id\t: 1
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processor\t: 3
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vendor_id\t: CPU-VENDOR-NAME
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cpu family\t: X
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model\t\t: YY
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model name\t: ANOTHER\tCPU MODEL WITH STRANGE S P A C E S
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physical id\t: 1
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"""),
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create=True
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)
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def test_spaces_squeezing(self):
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"""Test name sanitizing, needed on some platforms"""
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self.assertDictEqual(
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CPU().value,
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{'CPU MODEL NAME': 1}
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def test_parse_proc_cpuinfo_multiple_inconsistent_entries(self):
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"""
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Test `/proc/cpuinfo` parsing with multiple CPUs sharing same physical ids (unlikely).
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Also check our model name normalizations applied on white characters.
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"""
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self.assertListEqual(
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CPU._parse_proc_cpuinfo(), # pylint: disable=protected-access
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[
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{
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'CPU-MODEL-NAME': 1,
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'ANOTHER-CPU-MODEL': 1
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},
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{
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'ANOTHER CPU MODEL WITH STRANGE S P A C E S': 2
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}
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]
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)
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@patch(
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@ -132,29 +172,103 @@ model name\t: CPU MODEL\t NAME
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side_effect=PermissionError(),
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create=True
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)
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def test_parse_proc_cpuinfo_unreadable_file(self, _):
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"""Check behavior when `/proc/cpuinfo` could not be read from disk"""
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self.assertListEmpty(CPU._parse_proc_cpuinfo()) # pylint: disable=protected-access
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@patch(
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'archey.entries.cpu.check_output',
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return_value="""\
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side_effect=[
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"""\
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Architecture: x86_64
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CPU op-mode(s): 32-bit, 64-bit
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Byte Order: Little Endian
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CPU(s): 4
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On-line CPU(s) list: 0-3
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Thread(s) per core: X
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Core(s) per socket: Y
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Thread(s) per core: 1
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Core(s) per socket: 4
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Socket(s): 1
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NUMA node(s): 1
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Vendor ID: CPU-VENDOR-NAME
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CPU family: Z
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Model: \xde\xad\xbe\xef
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Model name: CPU-MODEL-NAME-WITHOUT-PROC-CPUINFO
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""")
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def test_proc_cpuinfo_unreadable(self, _, __):
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"""Check Archey does not crash when `/proc/cpuinfo` is not readable"""
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self.assertDictEqual(
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CPU().value,
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{'CPU-MODEL-NAME-WITHOUT-PROC-CPUINFO': 4}
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)
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Model name: CPU-MODEL-NAME
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""",
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"""\
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Architecture: x86_64
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CPU op-mode(s): 32-bit, 64-bit
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Byte Order: Little Endian
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CPU(s): 2
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On-line CPU(s) list: 0-1
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Thread(s) per core: 1
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Core(s) per socket: 2
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Socket(s): 1
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NUMA node(s): 1
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Vendor ID: CPU-VENDOR-NAME
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CPU family: Z
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Model: \xde\xad\xbe\xef
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Model name: CPU-MODEL-NAME
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Architecture: x86_64
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CPU op-mode(s): 32-bit, 64-bit
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Byte Order: Little Endian
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CPU(s): 4
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On-line CPU(s) list: 0-3
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Thread(s) per core: 2
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Core(s) per socket: 2
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Socket(s): 1
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NUMA node(s): 1
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Vendor ID: CPU-VENDOR-NAME
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CPU family: Z
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Model: \xde\xad\xbe\xef
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Model name: ANOTHER-CPU-MODEL
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""",
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"""\
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Architecture: x86_64
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CPU op-mode(s): 32-bit, 64-bit
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Byte Order: Little Endian
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CPU(s): 16
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On-line CPU(s) list: 0-15
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Thread(s) per core: 2
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Core(s) per socket: 4
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Socket(s): 2
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NUMA node(s): 2
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Vendor ID: CPU-VENDOR-NAME
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CPU family: Z
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Model: \xde\xad\xbe\xef
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Model name: CPU-MODEL-NAME
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"""])
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def test_parse_lscpu_output(self, _):
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"""
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Test model name parsing from `lscpu` output.
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See issue #29 (ARM architectures).
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`/proc/cpuinfo` will not contain `model name` info.
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`lscpu` output will be used instead.
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"""
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with self.subTest('Simple unique CPU.'):
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self.assertListEqual(
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CPU._parse_lscpu_output(), # pylint: disable=protected-access
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[{'CPU-MODEL-NAME': 4}]
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)
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with self.subTest('Two CPUs, 1 socket.'):
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self.assertListEqual(
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CPU._parse_lscpu_output(), # pylint: disable=protected-access
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[
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{'CPU-MODEL-NAME': 2},
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{'ANOTHER-CPU-MODEL': 4}
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]
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)
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with self.subTest('1 CPU, 2 sockets.'):
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self.assertListEqual(
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CPU._parse_lscpu_output(), # pylint: disable=protected-access
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[
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{'CPU-MODEL-NAME': 8},
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{'CPU-MODEL-NAME': 8}
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]
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)
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@HelperMethods.patch_clean_configuration
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def test_various_output_configuration(self):
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@ -162,15 +276,12 @@ Model name: CPU-MODEL-NAME-WITHOUT-PROC-CPUINFO
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cpu_instance_mock = HelperMethods.entry_mock(CPU)
|
||||
output_mock = MagicMock()
|
||||
|
||||
cpu_instance_mock.value = {
|
||||
'CPU-MODEL-NAME': 1,
|
||||
'ANOTHER-CPU-MODEL': 2
|
||||
}
|
||||
cpu_instance_mock.value = [
|
||||
{'CPU-MODEL-NAME': 1},
|
||||
{'ANOTHER-CPU-MODEL': 2}
|
||||
]
|
||||
|
||||
with self.subTest('Single-line combined output.'):
|
||||
if sys.version_info < (3, 6):
|
||||
self.skipTest("Cannot test behavior on Python < 3.6, skipping.")
|
||||
|
||||
CPU.output(cpu_instance_mock, output_mock)
|
||||
output_mock.append.assert_called_once_with(
|
||||
'CPU',
|
||||
@ -180,9 +291,6 @@ Model name: CPU-MODEL-NAME-WITHOUT-PROC-CPUINFO
|
||||
output_mock.reset_mock()
|
||||
|
||||
with self.subTest('Single-line combined output (no count).'):
|
||||
if sys.version_info < (3, 6):
|
||||
self.skipTest("Cannot test behavior on Python < 3.6, skipping.")
|
||||
|
||||
cpu_instance_mock.options['show_count'] = False
|
||||
|
||||
CPU.output(cpu_instance_mock, output_mock)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user